module dmux21_tb ();
parameter BITS = 4;
reg dS;
reg[BITS-1:0] dA,dB;
wire[BITS-1:0] mY;
integer loop,ecnt;
initial begin
  ecnt = 0;
  for (loop=0;loop<2**((BITS*2)+1);loop=loop+1) begin
    {dS,dA,dB} = loop;
    #5;
    if (dS===1'b1) begin
      if (mY!==dB) begin
        ecnt = ecnt + 1;
      end
    end
    else if (dS==1'b0) begin
      if (mY!==dA) begin
        ecnt = ecnt + 1;
      end
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module dmux21 verified!");
  end
  else begin
    $display("** Module dmux21 with errors! (%d)",ecnt);
  end
  $stop;
end
defparam dut.BITS = BITS;
dmux21 dut (iS,iA,iB,oY);
// or, dmux21 #(BITS) dut (iS,iA,iB,oY); // verilog2k1
endmodule