module sub_4b_tb ();
reg dB;
reg[3:0] dP,dQ;
wire mB;
wire[3:0] mS;
reg cB;
reg[3:0] cS;
integer loop,ecnt;
initial begin
  ecnt=0;
  for (loop=0;loop<512;loop=loop+1) begin
    {dB,dP,dQ} = loop;
    #5;
    {cB,cS} = dP - dQ - dB;
    if (mB!==cB||mS!==cS) begin
      ecnt = ecnt + 1;
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module sub_4b verified!");
  end
  else begin
    $display("** Module sub_4b with error(s)! (%d)",ecnt);
  end
  $stop;
end
sub_4b dut (dB,dP,dQ,mB,mS);
endmodule