module and_4b_tb ();
reg[3:0] dP,dQ;
wire[3:0] mY;
reg[3:0] cY;
integer loop,ecnt;
initial begin
  ecnt = 0;
  for (loop=0;loop<256;loop=loop+1) begin
    {dP,dQ} = loop;
    #5;
    cY = dP&dQ;
    if (mY!==cY) begin
      ecnt = ecnt + 1;
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module and_4b verified!");
  end
  else begin
    $display("** Module and_4b with error(s)! (%d)",ecnt);
  end
  $stop;
end
and_4b dut (dP,dQ,mY);
endmodule