module alu_4b_tb ();
reg[1:0] dS;
reg[3:0] dP,dQ;
wire[3:0] mY;
integer loop,ecnt;
initial begin
  ecnt=0;
  for (loop=0;loop<1024;loop=loop+1) begin
    {dS,dP,dQ} = loop;
    #5;
    if (dS===2'b00) begin // test add
      if (mY!==(dP+dQ)) begin
        ecnt = ecnt + 1;
      end
    end
    else if (dS===2'b01) begin // test sub
      if (mY!==(dP-dQ)) begin
        ecnt = ecnt + 1;
      end
    end
    else if (dS===2'b10) begin // test and
      if (mY!==(dP&dQ)) begin
        ecnt = ecnt + 1;
      end
    end
    else if (dS===2'b11) begin // test or
      if (mY!==(dP|dQ)) begin
        ecnt = ecnt + 1;
      end
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module alu_4b verified!");
  end
  else begin
    $display("** Module alu_4b with error(s)! (%d)",ecnt);
  end
  $stop;
end
alu_4b dut (dS,dP,dQ,mY);
endmodule