module cmp_1b (iA,iB,oGT,oLT,oEQ);
input iA,iB;
output oGT,oLT,oEQ;
wire oGT,oLT,oEQ, tGT, tLT;
assign tGT = iA & ~iB;
assign tLT = ~iA & iB;
assign oLT = tLT;
assign oGT = tGT;
assign oEQ = ~(tLT | tGT); // ~(iA ^ iB)
endmodule