module cmp_1b_tb ();
reg dA,dB;
wire mGT,mLT,mEQ;
integer loop,ecnt;
initial begin
  ecnt = 0;
  for (loop=0;loop<4;loop=loop+1) begin
    {dA,dB} = loop;
    #5;
    if (dA>dB) begin
      if (mGT!==1'b1||mLT!==1'b0||mEQ!==1'b0) begin
        ecnt = ecnt + 1;
      end
    end
    else if (dA<dB) begin
      if (mGT!==1'b0||mLT!==1'b1||mEQ!==1'b0) begin
        ecnt = ecnt + 1;
      end
    end
    else begin //if (dA==dB)
      if (mGT!==1'b0||mLT!==1'b0||mEQ!==1'b1) begin
        ecnt = ecnt + 1;
      end
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module cmp_1b verified");
  end
  else begin
    $display("** Module cmp_1b with error(s) (%d)",ecnt);
  end
  $stop;
end
cmp_1b dut (dA,dB,mGT,mLT,mEQ);
endmodule