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LAB PROJECT
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You are required to implement a soft-processor core (HDL-based) with the
following minimum requirements:
  - 8-bit microprocessor (instruction size, register size, etc.)
  - 8 general purpose registers
  - 8 ALU functions
  - basic instruction set
    = move data between registers
    = perform basic ALU operations
    = load register with immediate value

These requirements are necessary for submission and minimum grade B.
More functionality means better grades:
  - 16-bit/32-bit microprocessor
  - carry circuit for adder (>8b)
  - integer multiply/divide circuit (structural code - NOT behavior)
  - bit-level manipulation (towards microcontroller)
  - instruction fetch unit and memory interface

Note#1: Auto-0 for downloaded codes!

Note#2: This is a group assignment, but marks will be evaluated individually.

Assessment deliverables:

1) Verilog source files in a single ZIP file
- make sure only Verilog files are included in the file
- make sure all modules have each a proper testbench
- must be self-checking testbenches

2) Technical Document (Specifications)
- not more than 10 pages, no cover page (only list of members' names)
- content:
  = short summary of features
  = block diagram of design
  = list of instructions (description and op-code)

3) An online demonstration / Q&A
- not more than 20 minutes
- content:
  = short summary of what has been implemented
  = if completed, demonstrate running the top-level testbench
  = if NOT completed, demonstrate running component-level testbenches

PROJECT DUE: Lab Session@W14/14 (Item 1&2). Item 3 TBD.

Extra Info:
- each student may email in a contribution percentage information:
  = list all group members (specify project contribution percentage of each)
  = percentage values should total up to 100% (may use fraction e.g. 1/3)
Note: this is optional,but if a member decides to do this, please advise 
the others in group to do the same