module decode24 (iA,oY);
input[1:0] iA;
output[3:0] oY;
wire[3:0] oY;
assign oY[0] = ~iA[1] & ~iA[0];
assign oY[1] = ~iA[1] & iA[0];
assign oY[2] = iA[1] & ~iA[0];
assign oY[3] = iA[1] & iA[0];
endmodule