module dff_tb ();
parameter CLKP = 10;
reg dclk; // clock net
always begin
  #(CLKP/2) dclk = ~dclk;
end
// assume @+ve edge dff
// assume driver net is ddat
// should call this @-ve edge
reg ddat; // dff input
task dff_wr ;
  input integer dbit;
  begin
    ddat = dbit;
    $display("-- [%g] WR-dff:'%b' ",$time,ddat);
    #(CLKP/2); // setup time
    // should latch here
    #(CLKP/2); // hold time
    // 1-cycle
  end
endtask
// detect dff output
// can also use mdat!
always @(dut.odat) begin
  $write("[%05g] dffQ=%b\n",$time,dut.odat);
end
// 'main' block
wire mdat; // output signal
initial begin
  // reset condition
  dclk = 1'b1; //at tu=0, dclk is 1
  ddat = 1'b0;
  // start test
  #(CLKP/2); // wait for -ve edge
  dff_wr(1);
  #CLKP;
  // verify here? change ddat?
  #CLKP;
  dff_wr(0);
  #(CLKP*5);
  $stop;
end
dff dut (dclk,ddat,mdat);
endmodule