module dreg (iclk,wenb,renb,idat,odat);
parameter BITS = 4;
input iclk,wenb,renb;
input[BITS-1:0] idat;
output[BITS-1:0] odat;
wire[BITS-1:0] odat;
reg[BITS-1:0] tdat;
always @(posedge iclk)
begin
  if (wenb===1'b1) begin
    tdat = idat;
  end
end
defparam oenb.BITS = BITS;
zbuff oenb (renb,tdat,odat);
endmodule