module dffepc (iclk,ienb,ipre,iclr,idat,odat);
input iclk,ienb,ipre,iclr;
input idat;
output odat;
reg odat;
// synchronous pre/clr
always @(posedge iclk)
begin
  if (ipre===1'b1) begin
    odat = 1'b1;
  end
  else if (iclr===1'b1) begin
    odat = 1'b0;
  end
  else if (ienb===1'b1) begin
    odat = idat;
  end
end
endmodule