module dffepc_tb ();
parameter CLKP = 10;
reg dclk; // clock net
always begin
  #(CLKP/2) dclk = ~dclk;
end
reg denb, dpre, dclr, ddat;
task dffepc_reset ;
  begin
    dpre = 1'b1; // enable preset for 1 clk period
    $display("-- [%05g] dffepcPRE ",$time);
    #(CLKP);
    dpre = 1'b0;
  end
endtask
task dffepc_clear ;
  begin
    dclr = 1'b1; // enable clear for 1 clk period
    $display("-- [%05g] dffepcCLR ",$time);
    #(CLKP);
    dclr = 1'b0;
  end
endtask
task dffepc_write ;
  input integer dval;
  begin
    ddat = dval; // setup data for write
    denb = 1'b1; // enable write for 1 clk period
    $display("-- [%05g] WR-dffepc:'%b' ",$time,ddat);
    #(CLKP/2); // setup time
    #(CLKP/2); // hold time
    denb = 1'b0; // disable write
  end
endtask
wire mdat;
always @(mdat) begin
  $write("## [%05g] dffepcQ=%b\n",$time,mdat);
end
initial begin
  dclk = 1'b1; denb = 1'b0;
  dpre = 1'b0; dclr = 1'b0;
  #(CLKP/2); // wait for -ve edge
  dffepc_reset();
  dffepc_write(0);
  dffepc_write(1);
  #(CLKP*2);
  dffepc_write(4);
  dffepc_write(5);
  dffepc_clear();
  #(CLKP*1);
  dffepc_reset; // can leave out the () if no arg
  $finish;
end
dffepc dut (dclk,denb,dpre,dclr,ddat,mdat);
endmodule