module ringctr4_tb ();
parameter CLKP = 10;
reg dclk; // clock net
always begin
  #(CLKP/2) dclk = ~dclk;
end
reg drst;
task state_reset ;
  input integer clen;
  integer iter;
  begin
  $write("[%05g] Reset state machine ",$time);
  $display("for %g clock cycles",clen);
  drst = 1'b1;
  for (iter=0;iter<clen;iter=iter+1) begin
    #(CLKP);
  end
  drst = 1'b0;
  end
endtask
reg denb;
wire[3:0] mstt;
task state_cycle ;
  reg[3:0] curr;
  begin
    $display("[%05g] Running a cycle",$time);
    curr = mstt; denb = 1'b1;
    while (mstt==curr) #(CLKP);
    while (mstt!=curr) #(CLKP);
    denb = 1'b0;
    $display("[%05g] Completed cycle",$time);
  end
endtask
always @(mstt) begin // check changes in state
  case (mstt)
    4'b0001: $display("[%05g] STATE0",$time);
    4'b0010: $display("[%05g] STATE1",$time);
    4'b0100: $display("[%05g] STATE2",$time);
    4'b1000: $display("[%05g] STATE3",$time);
    default:
      $display("[%05g] STATEX (%04b)",$time,mstt);
  endcase
end
initial begin
  // reset code
  dclk = 1'b1; denb = 1'b0; drst = 1'b0;
  $display("[%05g] CurrentState:%b",$time,mstt);
  #(CLKP/2) state_reset(2);
  #(CLKP);
  #(CLKP) state_cycle();
  #(CLKP);
  #(CLKP) state_cycle();
  #(CLKP);
  $stop;
end
ringctr4 dut (dclk,drst,denb,mstt);
endmodule