module add_1b (iC,iP,iQ,oC,oS);
input iC,iP,iQ;
output oC, oS;
wire oC, oS, tP, tG, tP1, tP2, tS1, tS2, tX;
// just to show order DOES NOT matter
assign oS = tS1 | tS2; // iC ^ tP;
assign oC = tG | tX;
assign tG = iP & iQ;
assign tP1 = iP & ~iQ;
assign tP2 = ~iP & iQ;
assign tP = tP1 | tP2; // iP ^ iQ;
assign tS1 = iC & ~tP;
assign tS2 = ~iC & tP;
assign tX = iC & tP;
endmodule