module add_1b_tb ();
reg dC,dP,dQ;
wire mC,mS;
reg cC,cS;
integer loop,ecnt;
initial begin
  ecnt = 0;
  for (loop=0;loop<8;loop=loop+1) begin
    {dC,dP,dQ} = loop;
    #5;
    {cC,cS} = dC+dP+dQ; // or, do a truth table!
    if (mC!==cC||mS!==cS) begin
      ecnt = ecnt + 1;
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module add_1b verified!");
  end
  else begin
    $display("** Module add_1b with error(s)! (%d)",ecnt);
  end
  $stop;
end
add_1b dut (dC,dP,dQ,mC,mS);
endmodule