module add_4b_tb ();
reg dC;
reg[3:0] dP,dQ;
wire mC;
wire[3:0] mS;
reg cC;
reg[3:0] cS;
integer loop,ecnt;
initial begin
  ecnt=0;
  for (loop=0;loop<512;loop=loop+1) begin
    {dC,dP,dQ} = loop;
    #5;
    {cC,cS} = dP + dQ + dC;
    if (mC!==cC||mS!==cS) begin
      ecnt = ecnt + 1;
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module add_4b verified!");
  end
  else begin
    $display("** Module add_4b with error(s)! (%d)",ecnt);
  end
  $stop;
end
add_4b dut (dC,dP,dQ,mC,mS);
endmodule