module sub_1b (iB,iP,iQ,oB,oD);
input iB,iP,iQ;
output oB, oD;
wire oB, oD, tP, tG, tP1, tP2, tS1, tS2, tX;
assign oD = tS1 | tS2; // iB ^ tP;
assign oB = tG | tX;
assign tG = tP2; // ~iP & iQ;
assign tP1 = iP & ~iQ;
assign tP2 = ~iP & iQ;
assign tP = tP1 | tP2; // iP ^ iQ;
assign tS1 = iB & ~tP;
assign tS2 = ~iB & tP;
assign tX = tS1; // iB & ~tP;
endmodule