module sub_1b_tb ();
reg dB,dP,dQ;
wire mB,mD;
reg cB,cD;
integer loop,ecnt;
initial begin
  ecnt = 0;
  for (loop=0;loop<8;loop=loop+1) begin
    {dB,dP,dQ} = loop;
    #5;
    {cB,cD} = dP-dQ-dB; // or, do a truth table!
    if (mB!==cB||mD!==cD) begin
      ecnt = ecnt + 1;
    end
    #5;
  end
  if (ecnt==0) begin
    $display("-- Module sub_1b verified!");
  end
  else begin
    $display("** Module sub_1b with error(s)! (%d)",ecnt);
  end
  $stop;
end
sub_1b dut (dB,dP,dQ,mB,mD);
endmodule