Differences

This shows you the differences between two versions of the page.

--- archive:nmk206 [2025/04/09 11:38] – [Lab Session] azman
+++ archive:nmk206 [Unknown date] (current) – removed - external edit (Unknown date) 127.0.0.1
@@ Line 1: / Line 1: @@
-====== NMK206 - Computer Architecture ======
-This course is //Computer Architecture//, offered by the Faculty of Electronics Engineering & Technology (FKTEN) for Electronic Engineering Technology programs.
-Download [[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-windows.exe|ModelSim 20.1.1.720 (Intel FPGA Starter Edition) setup]] ([[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-windows.exe.sha1|SHA-1 checksum]]). Linux users can try [[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-linux.run|this]] ([[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-linux.run.sha1|SHA-1 checksum]]).
-**Video Guide(s)**
-[[https://www.youtube.com/playlist?list=PLKQoMxsWIO1zOp5-TVTkfbcTYp3wp-tJL|YouTube Playlist]]
-| <WRAP>
-ModelSim: Installation
-//**Note**:Available on [[https://youtu.be/oKgW5mtO8os|YouTube]].//
-//**Note**:{{archive:pgt206:nmk206_202425s2_howto_install_modelsim.mp4?linkonly|Local copy}} available.//
-</WRAP>  | {{youtube>oKgW5mtO8os?|ModelSim Installation}} |
-| <WRAP>
-ModelSim: Create Project
-//**Note**:Available on [[https://youtu.be/BneIhF8cKzQ|YouTube]].//
-//**Note**:{{archive:pgt206:nmk206_202425s2_modelsim_0create_project.mp4?linkonly|Local copy}} available.//
-</WRAP>  | {{youtube>BneIhF8cKzQ?|ModelSim:Create New Project}} |
-| <WRAP>
-ModelSim: Simulate Logic Cicuit
-//**Note**:Available on [[https://youtu.be/EPn5BKaFKpA|YouTube]].//
-//**Note**:{{archive:pgt206:nmk206_202425s2_modelsim_1simulate.mp4?linkonly|Local copy}} available.//
-</WRAP>  | {{youtube>EPn5BKaFKpA?||ModelSim:Simulate Logic Cicuit}} |
-===== Announcements =====
-[202503023] Welcome to NMK206 info page (for 007 lab sessions only)!
-===== Lab Session =====
-I am using [[https://en.wikipedia.org/wiki/Takahashi_method|Takahashi Method]] for these slides (Actually, I broke that method by adding diagrams and long codes because I think my students need them). You will find them hard to understand if you do not attend my sessions. So, that is the 'advantage' I gave to those who actually listen in class 8-)
-  * Lab Briefing {{ :archive:nmk206:my1lab00.pdf |Slides}}
-  * Intro to CAD Tools and HDL {{ :archive:nmk206:my1lab01.pdf |Slides}} {{ :archive:nmk206:nmk206_20250325_1intro_cad_hdl_fixmsg.mp4?linkonly |Online Session (Video)}}
-  * Verilog Basics {{ :archive:nmk206:my1lab02.pdf |Slides}} {{ :archive:nmk206:nmk206_20250325_2verilog_basics_fixmsg.mp4?linkonly |Online Session (Video)}}
-  * [Extra] {{ :archive:nmk206:nmk206_20250325_3comb_logic_partial.mp4?linkonly |Online Session (Video) (Partial... was stopped due to low number of students)}}
-  * Combinational Logic {{ :archive:nmk206:my1lab03.pdf |Slides (P1)}}
-//**note**: these are from 202324s2 academic session. they should be very similar this semester, but some details may be added or removed. i usually post an updated version at the end of the week.//
-  * Combinational Logic {{ :archive:pgt206:my1lab04.pdf |Slides (P2)}} {{ :archive:pgt206:my1lab05.pdf |Slides (P3)}} {{ :archive:pgt206:my1lab06.pdf |Slides (P4)}} {{ :archive:pgt206:my1lab07.pdf |Slides (P5)}}
-  * Sequential Logic {{ :archive:pgt206:my1lab08.pdf |Slides (P1)}} {{ :archive:pgt206:my1lab08_ext.pdf |Slides (P1x)}} {{ :archive:pgt206:my1lab09.pdf |Slides (P2)}}
-  * State Machine {{ :archive:pgt206:my1lab10.pdf |Slides}}
-  * Simple Digital System {{ :archive:pgt206:my1lab11.pdf |Slides}}
-==== Verilog Coding Rule ====
-This is the coding rule that I impose on my students. You will be penalized during assessments if it is not adhered to.
-  - One file for one module
-    * **RULE**: 1 file 1 module
-  - **File name must be the same as module name**
-    * **RULE**: file name === module name (.v)
-  - All circuit (module) must have a testbench (tb)
-    * tb is a also module (so, separate file)
-    * **RULE**: All module MUST have a testbench
-    * **RULE**: Tb name === module name + _tb
-  - Use Verilog95 module declaration
-    * Port list contain names only (separate input/output declaration)
-    * Port connection(s) MUST BE specified using ordered list
-    * **RULE**: Port connection(s) by ordered list ONLY!
-  - Modules for combinational logic should only use wire/assign statements
-    * reg/always reserved for sequential logic and testbench modules
-    * **RULE**: comb. logic use assign/wire only!
-  - Only basic logic gates are allowed
-    * Can only use AND/OR/INV in your logic implementation
-    * XOR logic is allowed for **lab project only**
-    * **RULE**: allowed operators AND, OR, INV
-  - Assign statements can only have ONE binary operator
-    * Multiple bitwise inverts (~) are ok (they are unary operators)
-    * **RULE**: 2-input logic gates ONLY
-  - ALL nets (wire/reg) MUST BE declared.
-    * some compiler may allow using without declaration
-    * for my assessments, they MUST BE declared
-    * **RULE**: All signals @wire must be declared!