archive:nmk206
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| - | ====== NMK206 - Computer Architecture ====== | ||
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| - | This course is //Computer Architecture//, | ||
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| - | Download [[https:// | ||
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| - | **Video Guide(s)** | ||
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| - | ModelSim: Installation | ||
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| - | ModelSim: Create Project | ||
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| - | ModelSim: Simulate Logic Cicuit | ||
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| - | ===== Announcements ===== | ||
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| - | [20250323] Welcome to NMK206 info page (for 007 lab sessions only)! | ||
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| - | [20250424] Soft reminder: Lab Assessment 1 @202500420-0800! | ||
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| - | ===== Lab Session ===== | ||
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| - | I am using [[https:// | ||
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| - | * Lab Briefing {{ : | ||
| - | * Intro to CAD Tools and HDL {{ : | ||
| - | * Verilog Basics {{ : | ||
| - | * [Extra] {{ : | ||
| - | * Combinational Logic {{ : | ||
| - | * Sequential Logic {{ : | ||
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| - | //**note**: these are from 202324s2 academic session. they should be very similar this semester, but some details may be added or removed. i usually post an updated version at the end of the week.// | ||
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| - | * Sequential Logic {{ : | ||
| - | * State Machine {{ : | ||
| - | * Simple Digital System {{ : | ||
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| - | ==== Verilog Coding Rule ==== | ||
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| - | This is the coding rule that I impose on my students. You will be penalized during assessments if it is not adhered to. | ||
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| - | - One file for one module | ||
| - | * **RULE**: 1 file 1 module | ||
| - | - **File name must be the same as module name** | ||
| - | * **RULE**: file name === module name (.v) | ||
| - | - All circuit (module) must have a testbench (tb) | ||
| - | * tb is a also module (so, separate file) | ||
| - | * **RULE**: All module MUST have a testbench | ||
| - | * **RULE**: Tb name === module name + _tb | ||
| - | - Use Verilog95 module declaration | ||
| - | * Port list contain names only (separate input/ | ||
| - | * Port connection(s) MUST BE specified using ordered list | ||
| - | * **RULE**: Port connection(s) by ordered list ONLY! | ||
| - | - Modules for combinational logic should only use wire/assign statements | ||
| - | * reg/always reserved for sequential logic and testbench modules | ||
| - | * **RULE**: comb. logic use assign/wire only! | ||
| - | - Only basic logic gates are allowed | ||
| - | * Can only use AND/OR/INV in your logic implementation | ||
| - | * XOR logic is allowed for **lab project only** | ||
| - | * **RULE**: allowed operators AND, OR, INV | ||
| - | - Assign statements can only have ONE binary operator | ||
| - | * Multiple bitwise inverts (~) are ok (they are unary operators) | ||
| - | * **RULE**: 2-input logic gates ONLY | ||
| - | - ALL nets (wire/reg) MUST BE declared. | ||
| - | * some compiler may allow using without declaration | ||
| - | * for my assessments, | ||
| - | * **RULE**: All signals @wire must be declared! | ||
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| - | ==== Lab Project (202425s2) Requirements ==== | ||
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| - | This is also shared in Google Doc format (link available in Google Classroom). | ||
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| - | <file text nmk206-202425s2_labproject.txt> | ||
| - | ----------- | ||
| - | LAB PROJECT | ||
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| - | You are required to implement a soft-processor core (HDL-based) with the | ||
| - | following minimum requirements: | ||
| - | - 8-bit microprocessor (instruction size, register size, etc.) | ||
| - | - 8 general purpose registers | ||
| - | - 8 ALU functions | ||
| - | - basic instruction set | ||
| - | = move data between registers | ||
| - | = perform basic ALU operations | ||
| - | = load register with immediate value | ||
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| - | These requirements are necessary for submission and minimum grade B. | ||
| - | More functionality means better grades: | ||
| - | - 16-bit/ | ||
| - | - carry circuit for adder (>8b) | ||
| - | - integer multiply/ | ||
| - | - bit-level manipulation (towards microcontroller) | ||
| - | - instruction fetch unit and memory interface | ||
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| - | Note#1: Auto-0 for downloaded codes! | ||
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| - | Note#2: This is a group assignment, but marks will be evaluated individually. | ||
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| - | Assessment deliverables: | ||
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| - | 1) Verilog source files in a single ZIP file | ||
| - | - make sure only Verilog files are included in the file | ||
| - | - make sure all modules have each a proper testbench | ||
| - | - must be self-checking testbenches | ||
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| - | 2) Technical Document (Specifications) | ||
| - | - not more than 10 pages, no cover page (only list of members' | ||
| - | - content: | ||
| - | = short summary of features | ||
| - | = block diagram of design | ||
| - | = list of instructions (description and op-code) | ||
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| - | 3) An online demonstration / Q&A | ||
| - | - not more than 20 minutes | ||
| - | - content: | ||
| - | = short summary of what has been implemented | ||
| - | = if completed, demonstrate running the top-level testbench | ||
| - | = if NOT completed, demonstrate running component-level testbenches | ||
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| - | PROJECT DUE: Lab Session@W14/ | ||
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| - | Extra Info: | ||
| - | - each student may email in a contribution percentage information: | ||
| - | = list all group members (specify project contribution percentage of each) | ||
| - | = percentage values should total up to 100% (may use fraction e.g. 1/3) | ||
| - | Note: this is optional, | ||
| - | the others in group to do the same | ||
| - | </ | ||
archive/nmk206.1747886667.txt.gz · Last modified: by azman