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--- archive:nmk206 [2025/06/18 08:18] – [Lab Code (202425s2) Archive] azman
+++ archive:nmk206 [2025/07/04 10:50] (current) – [NMK206 - Computer Architecture] azman
@@ Line 1: / Line 1: @@
 ====== NMK206 - Computer Architecture ======
-This course is //Computer Architecture//, offered by the Faculty of Electronics Engineering & Technology (FKTEN) for Electronic Engineering Technology programs.
+This course is //Computer Architecture//, offered by the Faculty of Electronics Engineering & Technology (FKTEN) for Electronic Engineering Technology programs. This page serves as an information hub, mainly for 007 lab sessions.
 Download [[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-windows.exe|ModelSim 20.1.1.720 (Intel FPGA Starter Edition) setup]] ([[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-windows.exe.sha1|SHA-1 checksum]]). Linux users can try [[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-linux.run|this]] ([[https://azman.unimap.edu.my/storage/ModelSimSetup-20.1.1.720-linux.run.sha1|SHA-1 checksum]]).
@@ Line 87: / Line 87: @@
 Complete template for a simple 4-bit processor core (as discussed during class) available {{ :archive:nmk206:nmk206-upcore_20250527.zip |here}}.
+==== Lab Code (202425s2) Extra ====
+Here is an example code to utilize the carry/borrow signals of our add/subtract modules at ALU level. You may use this to create add-with-carry and subtract-with-borrow functions (hint: you need a selector signal to 'enable' the carry/borrow in signals {iC} and {iB}).
 <file verilog alu_flag_4b.v>
@@ Line 111: / Line 115: @@
 dmux41 sel0 (iS,tA0,tA1,tL0,tL1,oY);
+endmodule
+</file>
+<file verilog alu_flag_4b_tb.v>
+module alu_4b_tb ();
+reg[1:0] dS;
+reg[3:0] dP,dQ,dF;
+wire[3:0] mF,mY;
+reg[3:0] cF,cY;
+integer loop, ecnt;
+initial begin
+  ecnt = 0;
+  // TASK: try to put dS assignment in a loop! => shorter code!
+  dS = 2'b00; // test add
+  for (loop=0;loop<512;loop++) begin
+    {dF[0],dP,dQ} = loop;
+    #5;
+    { cF[0],cY } = dF[0] + dP + dQ;
+    if (cY!=mY||cF[0]!==mF[0]) begin
+      ecnt = ecnt + 1;
+      $display("** Add error (%x+%x+%x=%x@%x|%x:%x)!",dP,dQ,dF[0],mY,cY,
+        mF[0],cF[0]);
+    end
+  end
+  dS = 2'b01; // test sub
+  for (loop=0;loop<512;loop++) begin
+    {dF[1],dP,dQ} = loop;
+    #5;
+    { cF[1],cY } = dP - dQ - dF[1];
+    if (cY!=mY||cF[1]!==mF[1]) begin
+      ecnt = ecnt + 1;
+      $display("** Sub error (%x-%x-%x=%x@%x)!",dP,dQ,dF[1],mY,cY,
+        mF[1],cF[1]);
+    end
+  end
+  dS = 2'b10; // test and
+  for (loop=0;loop<256;loop++) begin
+    {dP,dQ} = loop;
+    #5;
+    cY = dP & dQ;
+    if (cY!=mY) begin
+      ecnt = ecnt + 1;
+      $display("** And error (%x&%x=%x@%x)!",dP,dQ,mY,cY);
+    end
+  end
+  dS = 2'b11; // test or
+  for (loop=0;loop<256;loop++) begin
+    {dP,dQ} = loop;
+    #5;
+    cY = dP | dQ;
+    if (cY!=mY) begin
+      ecnt = ecnt + 1;
+      $display("** Or error (%x|%x=%x@%x)!",dP,dQ,mY,cY);
+    end
+  end
+  if (ecnt==0) begin
+    $display("-- Module alu_4b verified!");
+  end
+  else begin
+    $display("** Module alu_4b with %g error(s)!",ecnt);
+  end
+end
+alu_4b dut (dS,dP,dQ,dF,mF,mY);
 endmodule