This page is intended for the participants of 'Introduction to Verilog and ModelSim' training course (July 19-21, 2016).
Updated20160718: The course has been postponed to August 1-3, 2016.
Many electronic system design work involves Hardware Description Language (HDL) coding. Verilog HDL is one of the easiest HDL to learn and is the preferred language especially for entry-level engineers. This is because of its simplicity (e.g. as opposed to VHDL which is strongly typed) and its C-like syntax (which most engineering students would be familiar with). ModelSim is an industry-standard HDL simulation environment by Mentor Graphics® that is used (among others) for Integrated Circuit (IC) design, FPGA-based digital designs, or simply for logic verification.
This course is designed to provide introductory-level practical knowledge on using Verilog and ModelSim for simple digital logic/system design.
Upon completion of this course, the participants should be able to:
This course is designed for engineers, researchers, system designers, technical specialists, graduate students and individuals who are interested in developing fundamental skills on digital systems development, especially on FPGA platform.
Related keywords: HDL, Verilog, ModelSim, Digital Logic/Systems Design.
Sessions | Details | Materials | Notes |
---|---|---|---|
Session 1 |
| Mainly a theoretical session |
|
Session 2 |
| Step-by-step software session |
|
Session 3 & 4 |
| A more practical session (2 slots) |
|
Session 5 & 6 |
(This is optional and depends on participants' progress)
| A more practical session (2 slots) |