Lab Work 3 - Sequential Logic Circuits

This module consists of a few parts:

Implementing Sequential Logic

Sequential logic circuits mainly provides storage for a digital system. Thus, for example, it allows implementation of processes that need the previous state of a digital logic.

Only two basic types of sequential logic circuit:

Latch : level-triggered temporary storage device with 2 stable states
Flip-flop : edge-triggered storage device

Note: We will be using the button (@reset) switch (instead of the normal toggle DIP-switch). Try to find out why this is a better option.

Implementing Latches

For a basic latch, it needs to have the means to achieve any stable state (HI or LO) at its output and to maintain that output state.

S-R Latch

A basic S-R Latch:

Truth table:

			${overline{Q_n}}$
0	0	$Q_{n-1}$	${overline{Q_{n-1}}}$
0	1	0	1
1	0	1	0
1	1	0*	0*

Note: '*' indicates invalid condition

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

Notice that the invalid condition will happen when the S & R inputs are both at logic 1. In a real digital system, we need to prevent this from happening.

Gated S-R Latch

A gated S-R Latch:

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

Truth table for a S-R Latch:

				${overline{Q_n}}$
0	0	0	$Q_{n-1}$	${overline{Q_{n-1}}}$
0	1	0	$Q_{n-1}$	${overline{Q_{n-1}}}$
1	0	0	$Q_{n-1}$	${overline{Q_{n-1}}}$
1	1	0	$Q_{n-1}$	${overline{Q_{n-1}}}$
0	0	1	$Q_{n-1}$	${overline{Q_{n-1}}}$
0	1	1	0	1
1	0	1	1	0
1	1	1	1	1

Note:Output in BOLD is an invalid condition.

Gated D Latch

A gated D Latch:

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

Truth table for a gated D Latch:

			${overline{Q_n}}$
0	X	$Q_{n-1}$	${overline{Q_{n-1}}}$
1	0	0	1
1	1	1	0

Implementing Flip-flops

Unlike latches, flip-flops requires reference clock signal that is used to transfer whatever signal at its input to its internal storage (latch).

D Flip-flop

A D flip-flop (DFF) can be built using two opposite level-triggered gated D latches. This is known as a master slave DFF, as shown in figure below. Is this a positive or negative edge-triggered DFF?

Disclaimer: The image above is obtained from Wikipedia

Truth table for a positive edge-triggered DFF:

			${overline{Q_n}}$
0→1	0	0	1
0→1	1	1	0

The table for negative edge-triggered DFF onlly differs at CLK column with 1→0 instead of 0→1.

J-K Flip-flop

Truth table for a J-K Flip-flop:

				${overline{Q_n}}$
0	0	0→1	$Q_{n-1}$	${overline{Q_{n-1}}}$
0	1	0→1	0	1
1	0	0→1	1	0
1	1	0→1	${overline{Q_{n-1}}}$	$Q_{n-1}$

Notice that, unlike DFF, J-K FF has a toggle mode.

T Flip-flop

The DFF can easily be modified to act as a Flip-flop that toggles on clock edges - by simply connecting the output to the input.

Things To Do

THING1 Build an S-R Latch (use NOR gates) and verify.

THING2 Build a gated S-R Latch (use NAND gates) and verify.

THING3 Build a gated D Latch and verify.

THING4 Build a D Flip-flop (DFF) and verify.

THING5 Build a J-K Flip-flop and verify.

THING6 (optional) Try to verify the use of DFF as a frequency divider.

One-Shots and Oscillators

We will be using the versatile 555 timer as both a monostable multivibrator (one-shot) and an astable multivibrator (oscillator). The internals of a 555 IC is shown below.

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

The main internal components of a 555 timer are 2 voltage comparators that are configured by a voltage divider circuit that provides a trigger value of ${1/3}V_cc$ and a threshold value of ${2/3}V_cc$ . These values can be externally adjusted using the control voltage pin (5).

555 One-shot Operation

We just need a resistor and a capacitor for this (an extra decoupling capacitor is optional).

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

Initially, the circuit will settle down to its stable state.

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

When triggered, it will set the internal R-S latch, which consequently enables the circuit to charge the capacitor.

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

Once the capacitor is fully charged (actually, once the voltage is over threshold) and the trigger signal is deasserted, comparator A should cause the latch to reset and consequently cause the discharging of the capacitor.

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

Notice that the pulse width generated at the output pin should be around ${t_w}=1.1{R_1}{C_1}$

555 Oscillator Operation

This time we need an extra resistor.

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

This is how the the oscillator works - the capacitor is charged through the two resistors ( and ) when the internal transistor is off, and discharged through when transistor is on.

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

The frequency of the generated signal at the output pin should be ${f}={1.44/({R_1}+{2R_2}){C_1}}$ . The time that the output is at should be ${t_H}={0.7({R_1}+{R_2}){C_1}}$ , while the time for the output to be at GND should be ${t_L}={0.7{R_2}{C_1}}$ . Thus, the duty cycle is given by $({R_1+R_2}/{R1+2R_2})100%$ .

To get a duty cycle of less than 50%, we need a diode in order to bypass when charging the capacitor.

Disclaimer: The image above is extracted from resources available for Digital Fundamentals 11th Edition (Global Edition)

Thus, the duty cycle is now given by $({R_1}/{R1+R_2})100%$ .

Things To Do

THING1 Build a one-shot circuit that produces 1ms pulse. Determine a suitable R & C values. Verify.

THING2 Build an oscillator circuit that produces 1kHz (50% duty cycle) square-wave signal. Verify.

THING3 (Optional) Build an oscillator circuit that produces 50Hz signal, and ${t_H}=1ms$ . Verify.

Flip-flop ICs

We are going to look at samples of flip-flop IC:

D Flip-flop (DFF 7474: Dual D-FF positive-edge triggered, asynchronous preset & clear)
J-K Flip-flop (JKFF 7476: Dual JK-FF asynchronous preset & clear)
J-K Flip-flop (JKFF 74112: Dual JK-FF negative-edge triggered, asynchronous preset & clear)

Things To Do

THING1 Implement a 2-bit counter (asynchronous, continuously counts up).

THING2 (Optional) Implement THING1 with start/stop/reset button(s).

THING3 Implement a 4-bit counter (asynchronous, continuously counts up).

THING4 (Optional) Implement a 4-bit counter (asynchronous, continuously counts down).

THING5 Implement a 4-bit running light (Hint: Ring Counter - you need a reset switch for this).

Azman @UniMAP

Table of Contents

Lab Work 3 - Sequential Logic Circuits

Implementing Sequential Logic

Implementing Latches

S-R Latch

Gated S-R Latch

Gated D Latch

Implementing Flip-flops

D Flip-flop

J-K Flip-flop

T Flip-flop

Things To Do

One-Shots and Oscillators

555 One-shot Operation

555 Oscillator Operation

Things To Do

Flip-flop ICs

Things To Do